1. Field of the Invention
The present invention relates to a method for producing a semiconductor device and, more particularly, to a step of forming a channel stopper region under a field insulating:film formed by the so-called local oxidation of a semiconductor substrate such as silicon.
2. Description of the Prior Art
Increasing degrees of integration demand provision of more minuscule element isolation regions. There are know, as element isolation techniques, LOCOS (Local Oxidation of Silicon) and LOPOS (Local Oxidation of Poly Silicon). Even if the isolation regions are formed fine, it is require to prevent parasitic MOS transistors from being rendered conductive. For this purpose, channel stopper layers are further formed under the field insulating films formed by the local oxidation to thereby enhance the threshold voltages of the parasitic MOS transistors. According to these conventional element isolation processes, however, since the formation of the thick insulation layers by the local oxidation and implantation of an impurity for the formation of the channel stopper layers are conducted in a self-aligning manner, the formed channel stopper layers expand undesirably to make each of active regions small.
More specifically, according to a prior art as shown in FIG. 1(a) through FIG. 1(d), a silicon oxide film 2, a polycrystalline silicon film 3 and a silicon nitride film 4 are successively layered on a silicon substrate 1 in that order. Then, the polycrystalline silicon film 3 and the silicon nitride film 4 are selectively etched away (FIG. 1(a)).
Thereafter, boron ions 9 are implanted (FIG. 1(b)), after which local oxidation is carried out to form field insulating films 7 (FIG. 1(c)) and channel stopper layers 10. During this process, the channel stopper layers 10 extending lateral direction. The layers 2, 3 and 4 are then removed, followed by forming gate oxide films 11 and polysilicon gates 18. High impurity concentration layers 16 as source/drain regions are then formed to form MOS transistors (FIG. 1(d)) by using the gates 18 and field oxide layers 7 as a mask.
For this reason, as is apparent from FIG. 1(d), the respective parts of the P-type channel stopper layers 7 extended in lateral directions and the parts of the layers 16 form overlap regions 17. P.sup.+ -N.sup.+ functions are present in these overlap regions 17. As a result, the junction capacitance rises resulting in increase in a leakage current. If this method is applied to a dynamic memory device, the data storage characteristics of each memory cell are deteriorated.
Some techniques have been proposed to solve this problem. For example, Japanese Laid-Open Application No. Sho 64-68943 and Japanese Laid-Open Application No. Hei 1-297837 disclose such a method that involves implantation of boron ions into the substrate through field insulating films. The lateral expansion of the channel stopper is thereby suppressed.
However, this method causes boron ions further to be implanted into the substrate portions below the channel region of the transistor and below the source/drain regions. For this reason, the characteristics of the transistors are made changed and the junction capacitance is also increased.
The above drawback may be solved by the method as described in Japanese Laid-Open Application No. Sho 63-293850. The description on this method will be made below with reference to FIG. 2(a) through FIG. 2(f).
As shown in FIG. 2(a), a silicon substrate 1 is thermally oxidized to form an approximately 20 nm-thick silicon oxide film 2, followed by forming, as an antioxidant film or an oxidation-resist film, a silicon nitride film 4 in about 120 nm thick by the so-called CVD method. A polycrystalline silicon film 3 is then formed on the silicon nitride film 4 on which a second silicon nitride film 5 is then layered by CVD to a thickness of approximately 30 nm.
Photolithography is then used to leave the respective parts of the second silicon nitride film 5, polycrystalline silicon film 3 and first silicon nitride film 4 located on element formation regions, as shown in FIG. 2(b).
An approximately 30 nm-thick third silicon nitride film 6 is thereafter deposited over the entire surface by CVD. The anisotropic dry etching is then carried out to form sidewalls 6 made of silicon nitride film on the side surfaces of the first silicon nitride film 4, polycrystalline silicon film 3 and second silicon nitride film 5, as shown in FIG. 2(c). Thus, the silicon nitride sidewalls 6 cooperate with the silicon nitride films 4 and 5 to completely surround the polycrystalline silicon films 3. Accordingly, the polycrystalline silicon film 3 is protected from being oxidized against the subsequent thermal oxidation step.
Local oxidation is the conducted by using the first silicon nitride film 4, polycrystalline silicon film 3, second silicon nitride film 5 and silicon nitride sidewalls 6 as a mask. Thick field oxide films 7 are thereby formed in thickness of about 500 nm as element isolation regions, as shown in FIG. 2(c).
A polycrystalline silicon film is thereafter deposited over the entire surface, followed by performing the anisotropic dry etching. As a result, polycrystalline silicon sidewalls 8 are formed on the side surfaces of the respective nitrogen silicon sidewalls 6, as shown in FIG. 2(d).
By using the remaining silicon nitride film 4, polycrystalline silicon film 3, second silicon nitride film 5, silicon nitride sidewalls 6 and polycrystalline silicon sidewalls 8 as a mask, boron ions 9 are implanted to form P-type channel stopper layers 10. At this time, the polycrystalline silicon film 3 operates to prevent the penetration of the boron ions 9 into the silicon substrate 1. Accordingly, the channel stopper regions 10 are formed only under the field oxide layers 7, as shown in FIG. 2(e). The polycrystalline silicon film made sidewalls 8, silicon nitride sidewalls 6, second silicon nitride film 5, polycrystalline silicon film 3, first silicon nitride film 4 and silicon oxide film 2 are then removed.
As shown in FIG. 2(f), a gate insulation film 11 is thereafter formed in a thickness of approximately 20 nm, followed by patterning to form a contact hole 12. Gate electrodes 13 with a thickness of about 300 nm are then formed on the gate insulation film 11 by CVD. The gate electrodes 13 have a so-called polycide structure composed of a polycrystalline silicon layer and a refractory metal (a high-melting metal) silicide. By the well-known processes, the so-called LDD MOS transistors are formed having lightly doped layers 14 and highly doped layers 16. Thus, fine pattern field isolation regions 7 as well as fine channel stopper regions 10 are formed.
However, the dry etching for forming the polycrystalline silicon sidewalls 8 also etches partially the field insulating films 7 to reduce the film thickness thereof. For this reason, the threshold voltage of the parasitic MOS transistor is lowered. Furthermore, since the deposition of a layer and the etchback thereof are repeated twice to form the sidewalls 6 and 8, resulting in the complicated process. The yields of the products is thereby lowered and the cost is increased.